The present invention relates to a semiconductor device, a memory access control method, and a semiconductor device system.
Operation circuit, such as a CPU (Central Processing Unit), for example, accesses an external memory (a main memory), such as an SDRAM (Synchronous Dynamic Random Access Memory), and performs read or write of data. Here, in the operation circuit accessing the external memory, an access delay called latency occurs. The latency is one of performance indices of the external memory, and CAS (Column Address Strobe) latency, etc. are typical. The smaller latency is, the higher-speed access can be performed.
Usually, the external memory supports burst access in which a plurality of addresses are continuously accessed by designating one address in addition to random access in which the addresses are designated one by one, and in which access is repeated. The above-mentioned access delay occurs for each address designation. In burst access, if the continuously accessed plurality of addresses are addresses (hereinafter referred to as “target addresses”) that are actually going to be accessed from now, the number of address designation can be more decreased than in the random access. Therefore, the number of occurrence of the access delay also decreases, and access efficiency improves.
In Japanese Unexamined Patent Application Publication No. 1989-23355, there is disclosed a cache storage management method that measures a data amount of an accessed cache track, and sequentially switches a processing mode and a random access processing mode based on the data amount.